Verifying a Self-Timed Divider

This paper presents an approach to verifying timed designs based on reenement: rst, correctness is established for a speed-independent model; then, the timed design is shown to be a reenement of this model. Although this approach is less automatic than methods based on timed state space enumeration, it is tractable for larger designs. Our method is implemented using a proof checker with a built-in model checker for verifying properties of high-level models, a tautology checker for establishing reenement, and a graph-based timing veriication procedure for showing timing properties of transistor level models. We demonstrate the method by proving the timing correctness of Williams' self-timed divider.